This application claimed priority of foreign application of Republic of Korea 10-2005-002/389 filed Mar. 15, 2005.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a stepped gate, which can prevent the stepped gate from leaning and increase the channel length of the device, thus contributing to an increase in the degree of integration of the device, as well as a semiconductor device manufactured thereby.
2. Description of the Prior Art
Currently, as the size of a semiconductor device becomes smaller, it is more and more difficult to secure the capacity of a capacitor. Also, as the magnitude of electric field in the junction regions of a transistor becomes larger, it is more and more difficult to secure the refresh characteristics of a cell area. For this reason, a method is used which makes the effective channel length of a transistor long by the use of a three-dimensional cell other than a planar cell.
Particularly, a stepped gate structure was recently proposed which is obtained by forming a recess in a portion both sides of the substrate's active region and then forming a stepped gate on a portion of the active region extending from each edge of the non-recessed portion of the active region to a portion of the recess of the active region. This structure provides an increase in the effective channel length required for the operation of the gate, resulting in an increase in the threshold voltage and an improvement in the refresh characteristics.
FIGS. 1A to 1F are cross-sectional views for explaining each step of a method of manufacturing a semiconductor device having a stepped gate.
As shown in FIG. 1A, the pad oxide film 11 and the pad nitride film 12 are sequentially formed on the silicon substrate 10 having an active region and a field region. Then, the pad nitride film 12 is etched so as to expose the field region, and the pad oxide film 11 and the silicon substrate 10 are etched using the remaining pad nitride film 12 as an etch barrier so as to form the trench 13 in the field region. Then, on the resulting substrate, the gap-fill oxide 14 is formed to fill the trench 13.
As shown in FIG. 1B, the gap-fill oxide film 14 is subjected to chemical mechanical polishing (hereinafter, also referred to as “CMP”) until the pad nitride film 12 is exposed.
As shown in FIG. 1C, the remaining pad nitride film 12 and pad oxide film 11 are then removed to form the isolation film 14a, after which the hard mask oxide film 15 is formed on the active region of the substrate 10.
As shown in FIG. 1D, the hard mask oxide film 15 is then etched so as to expose both sides of the active region. Next, both exposed sides of the active region are etched using the remaining hard mask film 15 as an etch barrier so as to form a recess in the active region.
As shown in FIG. 1E, the remaining hard mask oxide film is then removed. Then, the gate oxide film 16 is formed on the active region of the substrate 10. Next, the doped polycrystalline silicon film 17, the tungsten silicide film 18 and the gate hard mask film 19 are sequentially formed on the entire surface of the substrate 10 including the gate oxide film 16.
As shown in FIG. 1F, the gate hard mask film 19 is then etched, leaving a gate pattern. Next, the tungsten silicide film 18, the doped polycrystalline film 17 and the gate oxide film 16 are selectively etched using the remaining gate hard mask film as an etch barrier, thus forming the stepped gate 20 on a portion of the active region extending from each of both edges of the non-recessed central portion and a portion of the recess of the active region.
Although not shown in the drawings, a thermal oxidation process is then performed on the substrate 10 including the gate 20, in order to recover from damage caused by the etching process for forming the gate 20.
However, in the method of manufacturing the semiconductor device having the stepped gate 20 according to the prior art, the volume of the doped polycrystalline film 17 and the tungsten silicide film 18 in the gate 20 shrinks in the high-temperature thermal oxidation process conducted after the formation of the gate 20. Also, since the thickness of a portion of the doped polycrystalline silicon film 17 and the tungsten silicide film 18 placed on the recessed portion of the substrate 10 is greater than the thickness of a portion of the doped polycrystalline silicon film 17 and the tungsten silicide film 18 placed on the non-recessed portion of the substrate 10, then the volume of a portion of the films 17 and 18 placed on the recessed portion of the substrate 10 shink more. Thus, the gates 20 lean inwardly towards the recessed portion of the substrate 10. Accordingly, the interval between the adjacent gates 20 becomes narrower, and thus, contact open failure in the formation of a landing plug contact may occur. Also, an interlayer Insulating film to be formed later may not completely fill the interval between the gates 20 so that the bridge between plugs can occur. As a result, the characteristics of the device will be deteriorated.
And, as the degree of integration of the device continuously increases, there is a limitation in increasing the channel length of the device. Therefore, it will be difficult to fabricate a highly integrated device by the above-described prior method.